1. Field of the Invention
The present invention relates to an inspection for defects of a semiconductor wafer, and specifically, to an inspection for small pattern defects and foreign objects.
2. Description of the Background Art
In recent inspections for defects of semiconductor wafers, various inspection devices have been developed, with the aim of achieving higher sensitivity and broader application. Since a defect is often specific to an individual process module, sensitivity is set on defect basis. Conventionally, wafers in an identical process for an identical device have been subjected to an inspection with the same sensitivity. In other cases, such sensitivity has been adjusted by operators.
When the color of one wafer appears uneven, the inspection accuracy is degraded. In Japanese Patent Laying-Open No. 2002-100660, an inspection device with high sensitivity is disclosed. The defect inspection device described in the publication includes an optics unit acquiring the overall image of a semiconductor wafer, a display device displaying the overall image, an image processing unit dividing the image into a plurality of areas by the degree of density of the circuit pattern to be displayed on the display device, and a circuit setting a threshold value for each area for identifying potential defects.
According to the defect inspection device described in this publication, a threshold value is set for each divided area. Accordingly, a false alarm due to uneven color will not be detected, and hence an inspection with high sensitivity can be realized.
On the other hand, if the defect inspection is performed with the same inspection sensitivity, then varying wafers affected by process variations are measured with an identical inspection recipe. As a result, the inspection sensitivity will vary, making the process management difficult. Further, it is difficult to inspect even one wafer with an identical sensitivity, due to the difference in pattern density, and in thickness incurred by process variations. Still further, if operators are to adjust such sensitivity, an enormous amount of time may be required.
The defect inspection device described in this publication divides a memory/logic merged LSI (Large Scale Integrated circuit) into a memory unit, a logic unit, a peripheral circuit unit such as interface unit, and the like, corresponding to areas on a chip. For each area, the design rules of interconnections may differ, and the degree of criticality of a defect may differ depending on, for example, the type of the pattern to be layered thereon. For example, since the design rules are the smallest in the memory unit, a small foreign object or an improper pattern shape possibly becomes a critical defect. Since design rules of the pattern are relatively large and intervals between patterns are wide in the peripheral circuit unit, the size of a critical defect is large as compared to the memory unit. In such less critical peripheral circuit unit, the sensitivity of the inspection is lowered to decrease the rate of false alarm detection. Thus, a different threshold value is set for each circuit in an area, and the same areas of different LSI chips are inspected with the same sensitivity. Accordingly, the difference related to one specific LSI chip will not affect the inspection.